Synthesis of Moore FSM with Expanded Coding Space

The proposed method is targeted on reduction of hardware amount in logic circuit of Moore finite-state machine implemented with programmable logic arrays (PLA). The method is based on using more than minimal amount of variables in codes of FSM internal states. The method includes two stages of state encoding. The second stage is connected with recoding of states inside each class of pseudoequivalent states. An example is given for proposed method application. KeywordsMoore FSM, graph-scheme of algorithm, pseudoequivalent states, PLA, logic circuit